Japanese Laid-Open Patent Publication No. 2012-191204 describes a wiring substrate that incorporates an electronic component such as a chip capacitor. The electronic component is arranged in a cavity formed in an interlayer insulation layer of the wiring substrate. Such a wiring substrate may be manufactured as described below.
First, a wiring layer including a pad is formed on a support substrate. Then, a given number of build-up wiring layers and interlayer insulation layers are alternately stacked upon one another. Further, a given interlayer insulation layer undergoes laser processing to form a cavity in the interlayer insulation layer. Then, the electronic component is arranged in the cavity, and the cavity is filled with an insulative insulation layer that entirely covers the electronic component. A wiring layer, which is electrically connected to the electronic component, is then formed on the insulation layer. Finally, the support substrate is removed.
In the wiring substrate described above, the electronic component is mounted on a metal heat dissipation plate in the cavity of the interlayer insulation layer. In such a wiring substrate, only one side of the electronic component can be electrically connected to other components. This lowers the freedom of design. In this regard, there is still room for improvement.